跳转到主要内容
瑞萨电子 (Renesas Electronics Corporation)

瑞萨电子的时序产品组合已被 SiTime 收购。

数据手册、文档以及样品订购仍将通过 Renesas.com 官网提供,直至 2026 年底。如需新设计、采购、技术支持以及产品咨询,请访问 SiTime.com 官网或发送电子邮件至 [email protected]。预计于 2026 年底前全面过渡至 SiTime。

特性

  • Two LVPECL output pairs each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz, and 312.5MHz
  • Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz, and 155.52MHz
  • Attenuates the phase jitter of the input clock by using a low-cost pullable fundamental mode VCXO crystal
  • VCXO PLL bandwidth can be optimized for jitter attenuation and reference tracking using an external loop filter connection
  • FemtoClock frequency multiplier provides a low-jitter, high-frequency output
  • Absolute pull range: 50ppm
  • FemtoClock VCO frequency: 625MHz
  • RMS phase jitter at 125MHz, using a 25MHz crystal (12kHz - 20MHz): 0.25ps (typical) and 0.35ps (maximum)
  • 3.3V supply voltage
  • -40 °C to 85 °C ambient operating temperature
  • Available in lead-free (RoHS 6) package

描述

The 813N252I-09 is a PLL-based synchronous multiplier optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock® frequency multiplier that provides the low jitter, high-frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET, and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package and supports the industrial temperature range.

Download the Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262 white paper

当前筛选条件