特性
- Twenty-four LVCMOS outputs, 7Ω typical output impedance
- Selectable differential clock input pairs for redundant clock applications
- CLKx, nCLKx pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
- Maximum output frequency: 167MHz
- Translates any differential input signal (LVPECL, LVHSTL, LVDS) to LVCMOS without external bias networks
- Translates any single-ended input signal to LVCMOS with resistor bias on nCLK input
- Multiple output enable pins for disabling unused outputs in reduced fanout applications
- Output skew: 275ps (maximum)
- Part-to-part skew: 600ps (maximum)
- Bank skew: 150ps (maximum)
- Propagation Delay: 4.3ns (maximum)
- 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
描述
The 8344 is a low voltage, low skew, 1-to-24 Differential-to-LVCMOS Fanout Buffer. The 8344 is designed to translate any differential signal levels to LVCMOS levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock input. The dual clock inputs also facilitate board level testing. 8344 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 8344 ideal for those clock distribution applications demanding well defined performance and repeatability.
