特性
- Twenty-two differential HSTL outputs each with the ability to drive 50? to ground
- Selectable differential CLK, nCLK or LVPECL clock inputs
- CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
- PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
- Maximum output frequency: 500MHz
- Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to HSTL levels with resistor bias on nCLK input
- Output skew: 80ps (maximum)
- Part-to-part skew: 700ps (maximum)
- Jitter, RMS: 0.04ps (typical)
- LVPECL and HSTL mode operating voltage supply range: VDD = 3.3V ± 5%, VDDO = 1.6V to 2V, GND = 0V
- 0°C to 85°C ambient operating temperature
8524 - Block Diagram
描述
The 8524 is a low skew, 1-to-22 Differential-to-HSTL Fanout Buffer . The 8524 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the OE pin. The 8524's low output and part-to-part skew characteristics make it ideal for workstation, server, and other high performance clock distribution applications.
