特性
- Two 1:4, low skew, low additive jitter LVDS fanout buffers
- Two differential clock inputs
- Differential pairs can accept the following differential input levels: LVDS and LVPECL
- Maximum input clock frequency: 2GHz
- Output bank skew: 35ps, (maximum)
- Propagation delay: 300ps, (maximum)
- Low additive RMS phase jitter, 156.25MHz (10kHz to 20MHz): 105fs, (maximum)
- 2.5V supply voltage
- Lead-free (RoHS 6) 28-lead VFQFN package
- -40 °C to 85 °C ambient operating temperature
8SLVD2104 - Block Diagram
描述
The 8SLVD2104 is a high-performance differential dual 1:4 LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD2104 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD2104 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two independent buffers with four low-skew outputs each are available. The integrated bias voltage generators enable easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
产品参数
| 属性 | 值 |
|---|---|
| Temp. Range (°C) | -40 to 85°C |
| Product Category | Clock Buffers & Drivers, RF Buffers |
封装选项
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 5.0 x 5.0 x 0.8 | 28 | 0.5 |
