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2.5V/3.3V Differential LVPECL 2x2 Clock Switch And Fanout Buffer

封装信息

CAD 模型:View CAD Model
Pkg. Type:TQFP
Pkg. Code:PRG32
Lead Count (#):32
Pkg. Dimensions (mm):7.0 x 7.0 x 1.4
Pitch (mm):0.8

环境和出口类别

Pb (Lead) FreeYes
ECCN (US)EAR99
HTS (US)8542.39.0090
Moisture Sensitivity Level (MSL)3

产品属性

Pkg. TypeTQFP
Lead Count (#)32
Pb (Lead) FreeYes
Carrier TypeTray
Core Voltage (V)2.5V, 3.3V
FunctionBuffer, Multiplexer
Input Freq (MHz)3000
Input TypeLVPECL
Inputs (#)2
Length (mm)7
MOQ250
Moisture Sensitivity Level (MSL)3
Output Banks (#)2
Output Freq Range (MHz)3000
Output Skew (ps)50
Output TypeLVPECL
Output Voltage (V)2.5V, 3.3V
Outputs (#)6
Package Area (mm²)49
Pb Free Categorye3 Sn
Pitch (mm)0.8
Pkg. Dimensions (mm)7.0 x 7.0 x 1.4
Qty. per Carrier (#)250
Qty. per Reel (#)0
Requires Terms and ConditionsDoes not require acceptance of Terms and Conditions
Tape & ReelNo
Temp. Range (°C)0 to 70°C
Thickness (mm)1.4
Width (mm)7

描述

MC100ES6254 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to 3.0 GHz. Typical applications for the MC100ES6254 are primary clock distribution, switching and loopback systems of high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed communication systems. Primary purpose of the MC100ES6254 is high-speed clock switching applications. In addition, the MC100ES6254 can be configured as single 1:6 or dual 1:3 LVPECL fanout buffer for clock signals, or as loopback device in high-speed data applications. The MC100ES6254 can be operated from a 3.3 V or 2.5 V positive supply without the requirement of a negative supply line.