封装信息
| CAD 模型: | View CAD Model |
| Pkg. Type: | PLCC |
| Pkg. Code: | PLG28 |
| Lead Count (#): | 28 |
| Pkg. Dimensions (mm): | 11.5 x 11.5 x 3.63 |
| Pitch (mm): | 1.27 |
环境和出口类别
| Pb (Lead) Free | Yes |
| ECCN (US) | EAR99 |
| HTS (US) | 8542.39.0090 |
| Moisture Sensitivity Level (MSL) | 3 |
产品属性
| Pkg. Type | PLCC |
| Lead Count (#) | 28 |
| Pb (Lead) Free | Yes |
| Carrier Type | Tube |
| C-C Jitter Max P-P (ps) | 250 |
| Core Voltage (V) | 5 |
| Feedback Input | Yes |
| Input Freq (MHz) | 35 - 35 |
| Input Type | TTL |
| Inputs (#) | 2 |
| Length (mm) | 11.5 |
| MOQ | 114 |
| Moisture Sensitivity Level (MSL) | 3 |
| Output Banks (#) | 8 |
| Output Freq Range (MHz) | 14 - 35 |
| Output Signaling | TTL |
| Output Skew (ps) | 500 |
| Output Type | TTL |
| Output Voltage (V) | 5 |
| Outputs (#) | 8 |
| Package Area (mm²) | 132.3 |
| Pb Free Category | e3 Sn |
| Pitch (mm) | 1.27 |
| Pkg. Dimensions (mm) | 11.5 x 11.5 x 3.63 |
| Prog. Clock | No |
| Qty. per Carrier (#) | 38 |
| Qty. per Reel (#) | 0 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Temp. Range (°C) | 0 to 70°C |
| Thickness (mm) | 3.63 |
| Width (mm) | 11.5 |
有关 QS5917T 的资源
描述
The QS5917T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: Q0-Q4, 2xQ, Q/2, Q5. Careful layout and design insures < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5917T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. In addition, TTL level outputs reduce clock signal noise. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The VCO can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5917T is designed for use in high-performance workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227.