RRG50120-B10

The RRG5012X-A00 is a second-generation Multiplexing Registering Clock Driver (MRCD) used on DDR5 MRDIMMs. Its primary function is to buffer the Command/Address (CA) bus, chip selects, and clock between the host controller and the DRAMs. It also creates a BCOM bus that controls the data buffers. The RRG5012X-A00 contains two separate channels with some common logic such as clocking, but which otherwise operate independently of each other. For each channel, the host interface is a 7-bit + parity/CRC CA bus with two chip-select inputs, running at single or double data rate and 1x or 2x the DRAM frequency.

Both Mux Mode and Rank Mode are supported. In Mux Mode, up to two ranks per each of two multiplexed pseudo-channels are supported, allowing simultaneous operation in the same direction. The RRG5012X-A00 demultiplexes the pseudo-channels and transmits each to a separate DRAM output interface. Rank Mode does not use pseudo-channels and operates as a four-rank LRDIMM.

Each DRAM interface is a 14-bit single data rate CA bus output with a chip-select. The RRG5012X-A00 also transcodes commands from the CA bus onto a per-channel BCOM bus for data buffer control. The RRG5012X-A00 has a common clock input and PLL, but produces eight separate clock pairs to the DRAM channels.