RL78/G16 快速原型开发板

AI 生成的摘要: Fast Prototyping Boards for RL78/G15 and G16 disable using the reset pin as an I/O port via option byte settings, causing inability to write or debug via COM port after programming with PORTSELB = 0. This occurs because the reset pin, required for entering Flash Memory Programming Mode, functions as a port during COM connection, preventing flash programming. Recovery involves rewriting option bytes to PORTSELB = 1 using an IDE, Renesas Flash Programmer, or a dedicated recovery application that holds the reset pin low during connection to enable flash erase and rewrite operations.

AI 生成的摘要: The document explains handshake-based SPI slave communication using the serial array unit (SAU) in RL78/G16 microcontrollers. It details how the slave device uses chip select (CS) and BUSY signals to synchronize and communicate with the master via clock-synchronous serial interface (CSI). Communication occurs in 1 ms slots, supporting commands such as status check, transmit, receive, and transmit/receive. The BUSY signal indicates slave readiness, ensuring proper handshake during data transfer. Peripheral functions like serial array unit, port pins, and external interrupts facilitate this communication. Timing charts illustrate command execution and data flow between master and slave.

AI 生成的摘要: The document explains how to use the fixed-cycle interrupt and alarm interrupt functions of the RL78/G16 Realtime Clock 2 (RTC2). It details setting the RTC2 to display time on an LCD and control output ports, including toggling port P12 every 0.5 seconds and triggering an alarm interrupt on port P15 five seconds after a set time. The document covers initialization of RTC2, I/O ports, serial interface IICA0 for LCD communication, and LED control. It also specifies operation conditions, hardware configuration, and software flowcharts for implementing these functions effectively.

AI 生成的摘要: Modbus communication operates using a single-master/multi-slave architecture over serial interfaces, primarily Modbus ASCII and Modbus RTU modes. Modbus ASCII sends data as ASCII characters, making parsing easier but increasing transmission time, while Modbus RTU transmits binary data, reducing transmission time but requiring precise timing for parsing. The protocol supports up to 247 slaves, each with a unique address, and commonly uses RS-485 physical layers. The RL78 microcontroller combined with Renesas RS-485 transceivers enables efficient Modbus communication for industrial automation, supporting low-power operation and I/O control. The document details hardware and software configurations, including UART settings, timing measurements, and interrupt handling for both master and slave modes in ASCII and RTU formats.

AI 生成的摘要: The Timer Array Unit (TAU0) measures pulse intervals by detecting rising and falling edges on the TI00 input pin, capturing timer counts to determine high-level and low-level pulse widths. Measurement results store in on-chip RAM. The process uses capture end interrupts to ensure accurate timing, discards invalid short pulses, and repeats measurements multiple times. Initialization involves setting TAU0 channel 0 to capture mode with both-edge detection and enabling interrupts. The sample code operates under specified hardware and software conditions, including RL78/G16 MCU, 16 MHz clock, and various development environments.

AI 生成的摘要: The document details the implementation of slave transmission and reception using the RL78/G16 serial interface IICA in a single-master I2C system. It covers slave address handling, data transmission, and reception protocols, including register address specifications and communication timing. The slave device supports reading and writing multiple bytes within a defined serial RAM area. The document also explains IIC communication timing charts, interrupt handling, and control registers essential for managing data flow and acknowledgements between master and slave devices.

AI 生成的摘要: The document explains how to implement master transmission and reception using the RL78/G16 microcontroller's serial interface IICA in a single-master system. It details address transmission, data transmission, and reception procedures, assuming slaves with specific addressable registers and serial RAM. The master selects slaves by their unique 7-bit addresses and communicates through IIC protocol timing and control signals. It includes hardware and software configurations, timing charts, sample code, and peripheral function usage for effective IIC communication.