概览

随着对蜂窝服务带宽的要求越来越高，全球对 5G 多输入多输出（MIMO）解决方案的需求也越来越高。 该系统实现了 5G MIMO 所需的射频链和时钟树。

系统优势 ：

  • Sub-6GHz 器件面向小信号射频链，从 RF 天线到 ADC 来接收信号（Rx），以及从 DAC 到 PA 来传输信号（Tx）
  • 同类产品中最佳的高级定时产品具有极低的相位噪声和杂散抖动
  • 支持输入时钟冗余、中高频时钟扇出、JESD204B/C 和 IEEE 1588，以增强通用公共无线电接口（eCPRI）
  • 提供单芯片同步和时钟生成

应用

  • 大规模 5G MIMO

成功产品组合交互框图

选择相应模块，寻找适合您设计的产品

4:3 ratio ASIC / FPGA Digital Front End JESD20 4B/C Transceiver with Feedback Path ASIC / FPGA Digital Front End JESD20 4B/C Transceiver with Feedback Path ASIC / FPGA Digital Front End JESD20 4B/C Transceiver with Feedback Path 32 X 2T2R (16 X 4T4R) JESD20 4B/C Transceiver with Feedback P... 32 X 2T2R (16 X 4T4R)JESD20 4B/C Transceiver with Feedback Path Sheet.181 Sheet.182 Undo Sheet.1 Sheet.2 Sheet.3 Sheet.4 EU099 EU099 EU099 EU112 Power Block Power Block Power Block Variable Gain Amplifiers (VGA) Variable Gain Amplifiers (VGA) Variable Gain Amplifiers (VGA) 64 Element Antenna Array 64 Element Antenna Array 64 Element Antenna Array Bias Controller Bias Controller Bias Controller RF RF Switch RFSwitch Sheet.73 Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.90 Sheet.93 Sheet.94 Sheet.95 Sheet.100 PA PA PA Matching Network Matching Network Matching Network Shunt Sheet.25 Sheet.26 Sheet.27 Sheet.60 Sheet.82 Sheet.83 Sheet.85 Sheet.86 Sheet.87 Sheet.88 Sheet.89 Sheet.92 PA PA PA Matching Network Matching Network Matching Network Shunt.108 Sheet.109 Sheet.110 Sheet.111 Sheet.113 Sheet.114 Sheet.115 Sheet.116 Sheet.117 Sheet.118 Sheet.119 Sheet.120 Sheet.126 Sheet.127 Sheet.129 Sheet.130 SyncE Tx Clock G.8262 Compl. HW Filtered SyncE Tx Clock G.8262 Compl. HW Filtered SyncE Tx Clock G.8262 Compl. HW Filtered (7.68 MHz) (7.68 MHz) (7.68 MHz) (491.52 MHz) (491.52 MHz) (491.52 MHz) RxA RxA RxA RxB RxB RxB TxB TxB TxB Tx Feedback Tx Feedback Tx Feedback TxA TxA TxA Sheet.165 Sheet.157 Sheet.158 Connector 1.171 Sheet.160 Connector 1.161 Sheet.162 Connector 1.163 Sheet.164 RF shows x2 channels for simplicity. This would be repeated 32-times for a 64T64R radio. RF shows x2 channels for simplicity. This would be repeated 3... RF shows x2 channels for simplicity. This would be repeated 32-times for a 64T64R radio. Sheet.167 Sheet.168 Sheet.169 Sheet.170 Sheet.175 Sheet.58 Undo Sheet.176 Sheet.177 Connector 1.171 Sheet.184 Sheet.185 Sheet.186 Sheet.187 Connector 1.188 Sheet.195 Sheet.196 Sheet.197 Sheet.198 Sheet.199 Sheet.200 Sheet.201 Sheet.202 Sheet.209 Sheet.210 Resistor - Fixed Transformer Line.841 Inductor Air Core.509 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Line.29 Inductor Air Core.212 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.205 Sheet.206 Sheet.207 Sheet.208 Sheet.211 Sheet.213 Sheet.214 Sheet.215 Sheet.216 Sheet.229 Sheet.228 Sheet.221 Sheet.218 Sheet.220 Sheet.222 Sheet.223 Sheet.224 Sheet.225 Sheet.226 Sheet.227 Sheet.230 Sheet.232 Sheet.233 Sheet.234 Sheet.235 Sheet.236 Sheet.237 Sheet.238 Sheet.239 Sheet.240 Sheet.241 Sheet.242 Sheet.244 Sheet.245 Sheet.246 Sheet.247 Sheet.248 Sheet.249 Sheet.250 Sheet.251 Sheet.252 Sheet.253 Sheet.254 Sheet.256 Sheet.257 Sheet.258 Sheet.259 Sheet.260 Sheet.261 Sheet.262 Sheet.263 Sheet.264 Sheet.265 8 Communication Lines B.795 8 8 8 8 Communication Lines B.795 8 8 8 Sheet.281 Sheet.282 4 4 4 4 Sheet.285 4 4 4 4 Sheet.288 Clock Clock Clock SYSREF SYSREF SYSREF Clock Clock Clock SYSREF SYSREF SYSREF Clock Matrix Network Clock Synchronizer Clock Matrix Network Clock Synchronizer Clock Matrix Network Clock Synchronizer Sheet.296 ASIC / FPGA Digital Front End ASIC / FPGA Digital Front End ASIC / FPGA Digital Front End ASIC / FPGA Digital Front End Sheet.304 Sheet.305 Sheet.306 Sheet.307 Sheet.308 SyncE Rx Clock SyncE Rx Clock SyncE Rx Clock Frequency Control Word Frequency Control Word Frequency Control Word Sheet.313 eC PRI Interface eC PRI Interface eC PRI Interface RF Amp RF Amp RF Amp RF-Amp RF Amp RF Amp RF Amp.322 RF Amp RF Amp RF-Amp.323 RF Amp RF Amp RF Amp.324 RF Amp RF Amp RF Amp.325 RF Amp RF Amp 1:8 Clock 1:8 SYSREF Component block.751 1:8 Clock 1:8 SYSREF 1:8 Clock 1:8 SYSREF 1:8 Clock 1:8 SYSREF 1:8 Clock 1:8 SYSREF 1:8 Clock 1:8 SYSREF Sheet.326 JESD JESD204B/C Clock Jitter Attenuator JESD204B/CClock Jitter Attenuator Sheet.309 Sheet.310 RF Sample Freq. Generation, Spurious Cleaning RF Sample Freq. Generation, Spurious Cleaning RF Sample Freq. Generation, Spurious Cleaning Fan Out Fan Out Fan Out

推荐产品

Variable Gain Amplifiers (VGA)
可变增益放大器 (VGA)

推荐产品

RF Amp
射频放大器

推荐产品

RF Amp
射频放大器

推荐产品

RF Amp
射频放大器

推荐产品

RF Amp
射频放大器

推荐产品

RF Amp
射频放大器

推荐产品

RF Amp
射频放大器

推荐产品

RF Switch
射频开关

推荐产品

Clock Matrix Network Clock Synchronizer
同步以太网和 IEEE 1588 时钟

推荐产品

1:8 Clock; 1:8 SYSREF
射频缓冲器

推荐产品

JESD204B/C Clock Jitter Attenuator
射频同步器 及 JESD204B/C 时钟抖动衰减器

Related Winning Combination

Power Block
Efficient power supply concept for 5G MIMO Radio RF / Timing and Small Cell Radio RF / Timing telecom applications.
View Diagram
Power Supply for 5G
5G 基础设施电源